Exemplary embodiments relate to a direct memory access controller and its operating method, and more particularly, relate to a direct memory access controller capable of performing a channel loop transmission operation and its operating method.
Services being realized at a super-highway information network-based information age may be developed toward multimedia services which enable humans to see and hear using characters, voices, and images. This may necessitate a system processor capable of processing mass data. In particular, the system processor may access a memory very frequently at transferring of mass data such as multimedia data, image data, and the like.
A system performance may be depended upon a data transfer speed between a peripheral device processing data and a memory device. A direct memory access (DMA) transfer technique may be used to improve the system performance. In the DMA transfer technique, a processor does not take part in data transfer. That is, data transfer may be made directly between the peripheral device and the memory device connected with a bus. This may be accomplished under the control of a DMA controller. In other words, in the DMA transfer technique, the DMA controller may charge a data transfer operation instead of the processor.
Recent systems may be configured such that a processor and a memory device (or, many memory devices) are connected with a plurality of peripheral devices. In this case, it may be needed that data transfer is made rapidly and efficiently between the memory device and the peripheral devices. This requirement may be satisfied by using a multi-channel DMA controller having a plurality of transfer channels. The multi-channel DMA controller may make data transfer between the memory and the peripheral devices using different channels. A DMA transfer of the DMA controller may be made by setting registers used to determine operations of the plurality of channels.
In general, to control the DMA transfer, a system processor may frequently set the registers of the DMA controller and may frequently process interrupts according to completion of the DMA transfer. In particular, when transferring mass data, the system processor may spend a lot of time on setting of the registers used to decide operations of channels. Further, the system processor may spend a lot of time on processing of interrupts according to transfer completion of the channels. Accordingly, the system performance may be lowered.